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| author |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2019-08-02 11:31:20 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2019-08-02 11:31:21 +0200 |
| commit | ab35c8a5b07ee70f8544a2f2a131153a6584cb53 (patch) | |
| tree | 38638110d8142889232c88206b13dfa77ef219b8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'msm-fixes-2019_08_01' of https://gitlab.freedesktop.org/drm/msm into drm-fixes (diff) | |
| parent | drm/i915: Only recover active engines (diff) | |
| download | wireguard-linux-ab35c8a5b07ee70f8544a2f2a131153a6584cb53.tar.xz wireguard-linux-ab35c8a5b07ee70f8544a2f2a131153a6584cb53.zip | |
Merge tag 'drm-intel-fixes-2019-08-02' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.3-rc3:
- GVT fixes
- Fix TBT aux powerwell
- Fix PSR2 training pattern duration
- Fix memory leak in runtime wakeref tracking
- Fix ICL memory bandwidth issue preventing planes from being enabled
- Fix OA mux configuration delays for accurate performance data
- Fix VLV/CHV DP audio cdclk frequency requirements
- Fix register whitelisting to fix a number of GL & Vulkan CTS tests
- Fix ICL perf register offsets
- Fix Gen11 Sampler Prefetch workaround, impacting dEQP tests
- Fix various gen2 tracepoints
- A number of GEM locking fixes addressing lockdep issues
- Fix idle engine reset, recover only active engines
- Fix incorrect MCR programming
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87d0hnncgo.fsf@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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