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| author |   Prike Liang <Prike.Liang@amd.com> | 2020-03-04 10:36:21 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 09:42:08 -0500 |
| commit | ab65a371dd5f5cba6bd9a58a1a6d4115a71cc5c9 (patch) | |
| tree | 811b1919b4ab5d53873b592d25ae11b47360d576 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/powerplay: fix pre-check condition for setting clock range (diff) | |
| download | wireguard-linux-ab65a371dd5f5cba6bd9a58a1a6d4115a71cc5c9.tar.xz wireguard-linux-ab65a371dd5f5cba6bd9a58a1a6d4115a71cc5c9.zip | |
drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions