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| author |   Weiyi Lu <weiyi.lu@mediatek.com> | 2019-03-05 13:05:45 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-04-11 13:29:19 -0700 |
| commit | acddfc2c261b3653ab1c1b567a427299bac20d31 (patch) | |
| tree | bdacafd8bc6ece8d1219198e7eb9d4fec6743a9e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data (diff) | |
| download | wireguard-linux-acddfc2c261b3653ab1c1b567a427299bac20d31.tar.xz wireguard-linux-acddfc2c261b3653ab1c1b567a427299bac20d31.zip | |
clk: mediatek: Add MT8183 clock support
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions