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| author |   Sung Joon Kim <Sungjoon.Kim@amd.com> | 2024-08-27 14:49:44 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-09-18 16:15:07 -0400 |
| commit | ae5100805f98641ea4112241e350485c97936bbe (patch) | |
| tree | d71cb0f4e1265d49115c572c35f9046c7fa2c476 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Clean up dsc blocks in accelerated mode (diff) | |
| download | wireguard-linux-ae5100805f98641ea4112241e350485c97936bbe.tar.xz wireguard-linux-ae5100805f98641ea4112241e350485c97936bbe.zip | |
drm/amd/display: Disable SYMCLK32_LE root clock gating
[WHY & HOW]
On display on sequence, enabling SYMCLK32_LE root clock gating
causes issue in link training so disabling it is needed.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions