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| author |   William Qiu <william.qiu@starfivetech.com> | 2023-09-22 14:28:34 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-09-30 09:58:30 +0100 |
| commit | af571133f7ae028ec9b5fdab78f483af13bf28d3 (patch) | |
| tree | cb477c7a1ce4e73986267c24fe35ed26e6709a8b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: starfive: Add JH7110 PWM-DAC support (diff) | |
| download | wireguard-linux-af571133f7ae028ec9b5fdab78f483af13bf28d3.tar.xz wireguard-linux-af571133f7ae028ec9b5fdab78f483af13bf28d3.zip | |
riscv: dts: starfive: add assigned-clock* to limit frquency
In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions