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| author |   Vince Hsu <vinceh@nvidia.com> | 2016-08-24 15:56:56 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2016-08-24 10:54:17 -0700 |
| commit | af7c388a9c2e5fdd36da6eaaa35fb86fb8aefd0b (patch) | |
| tree | 3ea7b4acd4c5c11f1e3531a64e12b3cc30120c36 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r8a7795: Fix SD clocks (diff) | |
| download | wireguard-linux-af7c388a9c2e5fdd36da6eaaa35fb86fb8aefd0b.tar.xz wireguard-linux-af7c388a9c2e5fdd36da6eaaa35fb86fb8aefd0b.zip | |
clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
the DIS power domain is during up-powergating process but the clamp to this
domain is not removed yet. That causes a timeout and aborts the power
sequence, although the PLLD/PLLD2 has already locked. To remove the false
alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
clocks as locked.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions