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| author |   Yash Shah <yash.shah@sifive.com> | 2020-12-10 15:58:02 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-01-07 17:28:24 -0800 |
| commit | af951c3a113bc2cc0419e39f5752ca77f7ddf228 (patch) | |
| tree | fa3152bb51e86e8858f61924ec36896612e5d4e5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv/mm: Prevent kernel module to access user memory without uaccess routines (diff) | |
| download | wireguard-linux-af951c3a113bc2cc0419e39f5752ca77f7ddf228.tar.xz wireguard-linux-af951c3a113bc2cc0419e39f5752ca77f7ddf228.zip | |
dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions