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| author |   Chen Wang <unicorn_wang@outlook.com> | 2023-11-24 14:26:02 +0800 |
|---|---|---|
| committer | Chen Wang <unicorn_wang@outlook.com> | 2024-07-09 08:19:52 +0800 |
| commit | b1240a39511b9206293b82ac372c5114d6e15821 (patch) | |
| tree | f77a2325aaa3553b48b1da70f20cee3b02d393e4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 6.10-rc1 (diff) | |
| download | wireguard-linux-b1240a39511b9206293b82ac372c5114d6e15821.tar.xz wireguard-linux-b1240a39511b9206293b82ac372c5114d6e15821.zip | |
riscv: dts: add clock generator for Sophgo SG2042 SoC
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions