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| author |   Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2017-07-13 14:06:53 +0300 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-07-27 16:00:18 +0200 |
| commit | b127daecc70896fce7a2b2ada2f43b9ba7868b92 (patch) | |
| tree | 784b209ecfb0907e08085acd9cb02f35e58ea413 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes (diff) | |
| download | wireguard-linux-b127daecc70896fce7a2b2ada2f43b9ba7868b92.tar.xz wireguard-linux-b127daecc70896fce7a2b2ada2f43b9ba7868b92.zip | |
arm64: dts: salvator-xs: Add VC6 clock generator
The VC6 is an I2C-controlled programmable clock generator, used on the
board to provide a display dot clock. Add it to DT.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions