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| author |   Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2024-03-18 14:00:25 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2024-03-20 10:51:12 -0700 |
| commit | b4985cce8136d1cd91fafac1ec9a6d90b774fd01 (patch) | |
| tree | 1f0c67de2081696ee3dbe55ff0a90261c153753a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/selftests: Pick correct caching mode. (diff) | |
| download | wireguard-linux-b4985cce8136d1cd91fafac1ec9a6d90b774fd01.tar.xz wireguard-linux-b4985cce8136d1cd91fafac1ec9a6d90b774fd01.zip | |
drm/i915/xelpg: Add Wa_14020495402
Disable clockgating for TDL SVHS fub.
v2: Implement in general render/compute wa's(MattR)
Bspec: 46045
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240318210025.562698-1-radhakrishna.sripada@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions