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| author |   Manasi Navare <manasi.d.navare@intel.com> | 2020-02-14 03:41:25 -0800 |
|---|---|---|
| committer |   Uma Shankar <uma.shankar@intel.com> | 2020-02-20 13:53:55 +0530 |
| commit | b50a1aa6e1e9471c4adc0589244d885496e5cd0c (patch) | |
| tree | 5e3a9d11675a91fa6f3b7be6206123ef2010441a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Introduce encoder->compute_config_late() (diff) | |
| download | wireguard-linux-b50a1aa6e1e9471c4adc0589244d885496e5cd0c.tar.xz wireguard-linux-b50a1aa6e1e9471c4adc0589244d885496e5cd0c.zip | |
drm/i915/dp: Compute port sync crtc states post compute_config()
This patch pushes out the computation of master and slave
transcoders in crtc states after encoder's compute_config hook.
This ensures that the assigned master slave crtcs have exact same
mode and timings which is a requirement for Port sync mode
to be enabled.
v3:
* Make crtc_state const, remove crtc state NULL init (Ville)
v2:
* Correct indentation
* Rename to intel_ddi_port_sync_transcoders (Ville)
* remove unwanted debug (Ville)
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200214114126.13192-2-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions