diff options
| author |   Pierre Gondois <pierre.gondois@arm.com> | 2022-10-31 10:20:16 +0100 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2022-11-28 01:23:11 +0100 |
| commit | b5d971cf170e09fffc25b58b0de3cfdb0a1c342d (patch) | |
| tree | e64958925d2d6c9fb7f1ca6405a8c7b56ce50d8d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: armada-3720-turris-mox: Add missing interrupt for RTC (diff) | |
| download | wireguard-linux-b5d971cf170e09fffc25b58b0de3cfdb0a1c342d.tar.xz wireguard-linux-b5d971cf170e09fffc25b58b0de3cfdb0a1c342d.zip | |
arm64: dts: Update cache properties for marvell
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions