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| author |   Tony Lindgren <tony@atomide.com> | 2018-12-12 15:46:16 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-12-12 17:50:14 -0800 |
| commit | b8222335938a9c6425b9f14e61c3ca67c8189dfc (patch) | |
| tree | 7171f928412da0b3482e68481292bbbebc92e36c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: Add missing ranges for dra7 mcasp l3 ports (diff) | |
| download | wireguard-linux-b8222335938a9c6425b9f14e61c3ca67c8189dfc.tar.xz wireguard-linux-b8222335938a9c6425b9f14e61c3ca67c8189dfc.zip | |
ARM: dts: Fix wrong address for omap5 sata phy
Looks like I missed converting the omap5 sata phy addresses to use offset
from the module base instead of full physical address.
While at it, we can also more it to be a direct child of the interconnect
target module, it is not really a child of the ocp2scp control device.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions