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| author |   Chris Brandt <chris.brandt@renesas.com> | 2018-12-18 12:05:54 -0500 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2019-01-23 10:06:18 +0100 |
| commit | bbbcd02b825529076951a37ee632cdb33df414c7 (patch) | |
| tree | 3d3b665064871df6c1de4d550ad7339f7bb5d881 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: r8a7779: Add HSCIF0/1 device nodes (diff) | |
| download | wireguard-linux-bbbcd02b825529076951a37ee632cdb33df414c7.tar.xz wireguard-linux-bbbcd02b825529076951a37ee632cdb33df414c7.zip | |
ARM: dts: r7s9210: Initial SoC device tree
Basic support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions