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| author |   Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> | 2024-01-04 14:44:34 +0100 |
|---|---|---|
| committer |   Alexandre Torgue <alexandre.torgue@foss.st.com> | 2024-01-25 16:03:46 +0100 |
| commit | bda732fda19365b7a7397d0d37090f6dc253232c (patch) | |
| tree | b210188eb5cf3f7a4db024df9edf27d60717290a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: stm32: lxa-tac: drive powerboard lines as open-drain (diff) | |
| download | wireguard-linux-bda732fda19365b7a7397d0d37090f6dc253232c.tar.xz wireguard-linux-bda732fda19365b7a7397d0d37090f6dc253232c.zip | |
ARM: dts: stm32: fix DSI peripheral clock on stm32mp15 boards
In RCC driver, 'DSI_K' is a kernel clock while 'DSI' has pclk4 as parent
clock, which means that it is an APB peripheral clock. Swap the clocks
in the DSI peripheral clock reference.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions