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| author |   Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:37 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:12 -0700 |
| commit | be5e8872b3fbc74b4a58a7e6a7e9fb7e8509eaf8 (patch) | |
| tree | a872de55aa8b885c836b83ce2bb240a8b70e40ab /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | irqchip/riscv-intc: Introduce Andes hart-level interrupt controller (diff) | |
| download | wireguard-linux-be5e8872b3fbc74b4a58a7e6a7e9fb7e8509eaf8.tar.xz wireguard-linux-be5e8872b3fbc74b4a58a7e6a7e9fb7e8509eaf8.zip | |
riscv: errata: Rename defines for Andes
Use "ANDES" rather than "ANDESTECH" to unify the naming
convention with directory, file names, Kconfig options
and other definitions.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-2-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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