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author | 2024-04-26 09:07:22 +1000 | |
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committer | 2024-04-26 09:07:28 +1000 | |
commit | bfed5b0257a98b32dd31778fd42ce19f9df26695 (patch) | |
tree | 288f069e07433c6126e823cf88e48e49444194f3 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'drm-xe-next-2024-04-23' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next (diff) | |
parent | drm/i915/dsi: pass display to register macros instead of implicit variable (diff) | |
download | wireguard-linux-bfed5b0257a98b32dd31778fd42ce19f9df26695.tar.xz wireguard-linux-bfed5b0257a98b32dd31778fd42ce19f9df26695.zip |
Merge tag 'drm-intel-next-2024-04-24' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-next
Core Changes:
- Some DP/DP_MST DRM helpers (Imre)
Driver Changes (i915 Display):
- PLL refactoring (Ville)
- Limit eDP MSO pipe only for display version 20 (Luca)
- More display refactor towards independence from i915 dev_priv (Jani)
- QGV/SAGV related refactor (Stanislav)
- Few MTL/DSC and a UHBR monitor fix (Imre)
- BXT/GLK per-lane vswing and PHY reg cleanup (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Zik0LKEtN1PwXXGb@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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