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author | 2020-03-16 17:54:53 +0100 | |
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committer | 2020-03-17 01:19:46 +0100 | |
commit | c0044dc7d692fc140a0e249ace632b9b8d5e3cce (patch) | |
tree | 858db690857bbd7828e0257c1bb49b9ab47d8e3b /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ARM: dts: rockchip: fix lvds-encoder ports subnode for rk3188-bqedison2qc (diff) | |
download | wireguard-linux-c0044dc7d692fc140a0e249ace632b9b8d5e3cce.tar.xz wireguard-linux-c0044dc7d692fc140a0e249ace632b9b8d5e3cce.zip |
ARM: dts: rockchip: rk3xxx: fix L2 cache-controller nodename
A test with the command below gives for example this error:
arch/arm/boot/dts/rk3066a-bqcurie2.dt.yaml:
l2-cache-controller@10138000: $nodename:0:
'l2-cache-controller@10138000'
does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Fix error by changing nodename to 'cache-controller'.
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/l2c2x0.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200316165453.3022-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions