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author | 2019-03-15 13:59:25 -0400 | |
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committer | 2019-03-27 22:43:04 -0500 | |
commit | c0415c8722a43aa3f97f24ab54334107c34f9290 (patch) | |
tree | ae36277c9107a7422eee8562c151501b88570433 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/amd/display: Populate macro_tile_size field for dml (diff) | |
download | wireguard-linux-c0415c8722a43aa3f97f24ab54334107c34f9290.tar.xz wireguard-linux-c0415c8722a43aa3f97f24ab54334107c34f9290.zip |
drm/amd/display: fix odm output gamma programming
Currently only top pipe gets output tf programmed. This change
makes all odm head pipes get output tf programmed.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions