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| author |   Isabel Zhang <isabel.zhang@amd.com> | 2020-01-27 10:57:16 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-02-11 15:09:18 -0500 |
| commit | c134c3cabae46a56ab2e1f5e5fa49405e1758838 (patch) | |
| tree | 1cfc6ddf14d0210a7dc0d7a40439ceb3b1ece9c5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Limit minimum DPPCLK to 100MHz. (diff) | |
| download | wireguard-linux-c134c3cabae46a56ab2e1f5e5fa49405e1758838.tar.xz wireguard-linux-c134c3cabae46a56ab2e1f5e5fa49405e1758838.zip | |
drm/amd/display: Add initialitions for PLL2 clock source
[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.
[How]
Initializations added for PLL2 when creating resources.
Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions