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| author |   Conor Dooley <conor.dooley@microchip.com> | 2023-06-17 19:08:14 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-06-17 19:19:21 +0100 |
| commit | c1362fd0f2fdebf5c56d505100ba37600b5c20a5 (patch) | |
| tree | d20854c0f267807ecb3aeab41bacd51543b7ab93 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: starfive: Add cpu scaling for JH7110 SoC (diff) | |
| parent | riscv: defconfig: enable T-HEAD SoC (diff) | |
| download | wireguard-linux-c1362fd0f2fdebf5c56d505100ba37600b5c20a5.tar.xz wireguard-linux-c1362fd0f2fdebf5c56d505100ba37600b5c20a5.zip | |
Merge patch series "Add Sipeed Lichee Pi 4A RISC-V board support"
Jisheng Zhang <jszhang@kernel.org> says:
Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.
Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.
This also pulls in -rc2, because of some maintainers re-jigging that
went on in the interim in commit 80e62bc8487b ("MAINTAINERS: re-sort
all entries and fields").
Link: https://lore.kernel.org/r/20230617161529.2092-1-jszhang@kernel.org
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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