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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2016-09-21 16:31:41 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-10-17 15:56:21 +0200 |
| commit | c1b5371b72644907a9b81a7cd8eabb32f04466d1 (patch) | |
| tree | 7caa39c8f428e6da950f893afd4de625a5604062 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r8a7796: Add I2C clocks (diff) | |
| download | wireguard-linux-c1b5371b72644907a9b81a7cd8eabb32f04466d1.tar.xz wireguard-linux-c1b5371b72644907a9b81a7cd8eabb32f04466d1.zip | |
clk: renesas: cpg-mssr: Always use readl()/writel()
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions