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| author |   Quentin Schulz <quentin.schulz@bootlin.com> | 2018-10-04 14:22:03 +0200 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2018-10-05 14:36:44 -0700 |
| commit | c2a90025ad09d830c8d8ae69f485eac6aaaa2472 (patch) | |
| tree | 0b8d7fb1597c9276e8a7a07929d79725fb7affd6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | net: mscc: ocelot: simplify register access for PLL5 configuration (diff) | |
| download | wireguard-linux-c2a90025ad09d830c8d8ae69f485eac6aaaa2472.tar.xz wireguard-linux-c2a90025ad09d830c8d8ae69f485eac6aaaa2472.zip | |
phy: add QSGMII and PCIE modes
Prepare for upcoming phys that'll handle QSGMII or PCIe.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions