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author | 2024-05-31 11:52:06 -0700 | |
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committer | 2024-05-31 11:52:06 -0700 | |
commit | c6cc9799b4c16b1bd42de35be563d4fa6ea43799 (patch) | |
tree | 2647b1495c5589037740c9b3c3d5ecdaed3294f5 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'bcachefs-2024-05-30' of https://evilpiepirate.org/git/bcachefs (diff) | |
parent | riscv: Fix fully ordered LR/SC xchg[8|16]() implementations (diff) | |
download | wireguard-linux-c6cc9799b4c16b1bd42de35be563d4fa6ea43799.tar.xz wireguard-linux-c6cc9799b4c16b1bd42de35be563d4fa6ea43799.zip |
Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A fix to avoid pt_regs aliasing with idle thread stacks on secondary
harts.
- HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot
issues on XIP systems with huge pages.
- An update to the uABI documentation clarifying that only scalar
misaligned accesses were grandfathered in as supported, as the vector
extension did not exist at the time the uABI was frozen.
- A fix for the recently-added byte/half atomics to avoid losing the
fully ordered decorations.
* tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fix fully ordered LR/SC xchg[8|16]() implementations
Documentation: RISC-V: uabi: Only scalar misaligned loads are supported
riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel
riscv: prevent pt_regs corruption for secondary idle threads
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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