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author | 2020-06-29 10:06:49 +0800 | |
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committer | 2020-07-15 12:45:28 -0400 | |
commit | c8466cc0d2a419e7659bff5161440741cb96ab1e (patch) | |
tree | 0ae6b6313369f73cd356f000a2d427a39bea7344 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/amdgpu: correct ta header v2 ucode init start address (diff) | |
download | wireguard-linux-c8466cc0d2a419e7659bff5161440741cb96ab1e.tar.xz wireguard-linux-c8466cc0d2a419e7659bff5161440741cb96ab1e.zip |
drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
V2: delete unneccessary white lines and refine implementation.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions