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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-12-01 13:34:21 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-05 10:32:26 -0800 |
| commit | c9435dbee119f42132af2c3fc0382d16bda32601 (patch) | |
| tree | 9dc826441db5a5948e1534fd8ee3388bdce4cd0a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | cxl/port: Add RCD endpoint port enumeration (diff) | |
| download | wireguard-linux-c9435dbee119f42132af2c3fc0382d16bda32601.tar.xz wireguard-linux-c9435dbee119f42132af2c3fc0382d16bda32601.zip | |
tools/testing/cxl: Add an RCH topology
In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint
the represents the memory expander. Unlike a VH topology there is no
CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this
as the CXL root object (ACPI0017 on ACPI based systems) targeting the
host-bridge as a dport, per usual, but then that dport directly hosts
the endpoint port.
Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd'
device instance as its immediate child.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/166993046170.1882361.12460762475782283638.stgit@dwillia2-xfh.jf.intel.com
Reviewed-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions