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| author |   Colin Ian King <colin.king@canonical.com> | 2019-10-23 12:28:09 +0100 |
|---|---|---|
| committer |   Maxime Ripard <mripard@kernel.org> | 2019-10-29 08:42:52 +0100 |
| commit | cdfc2e2086bf9c465f44e2db25561373b084a113 (patch) | |
| tree | 5541768f3b3232aa5f38ba3bd77e5e4194e45d34 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: sunxi: Fix operator precedence in sunxi_divs_clk_setup (diff) | |
| download | wireguard-linux-cdfc2e2086bf9c465f44e2db25561373b084a113.tar.xz wireguard-linux-cdfc2e2086bf9c465f44e2db25561373b084a113.zip | |
clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18
The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.
Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions