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| author |   Cong Dang <cong.dang.xn@renesas.com> | 2024-02-14 14:02:16 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-20 11:37:31 +0100 |
| commit | ce772318637261525ee868ccfeb17b1927fcd812 (patch) | |
| tree | 2b7577ee38cf4416785ef136cc8717510e1b18c2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r8a779h0: Add SDHI clock (diff) | |
| download | wireguard-linux-ce772318637261525ee868ccfeb17b1927fcd812.tar.xz wireguard-linux-ce772318637261525ee868ccfeb17b1927fcd812.zip | |
clk: renesas: r8a779h0: Add SYS-DMAC clocks
Add the module clocks used by the Direct Memory Access Controllers for
System (SYS-DMAC) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/0285ef5d0c0c9d232e196559c9130ab46733d7f7.1707915706.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions