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| author |   Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> | 2016-10-13 10:31:48 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2016-11-02 20:39:55 +0100 |
| commit | cf31bc71c0f8cdf9c6529ff49b4928ea27b652e2 (patch) | |
| tree | bd1546c863dba2a4a4be1b4177cd23f2de25f136 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: cpg-mssr: Fix inverted debug check (diff) | |
| download | wireguard-linux-cf31bc71c0f8cdf9c6529ff49b4928ea27b652e2.tar.xz wireguard-linux-cf31bc71c0f8cdf9c6529ff49b4928ea27b652e2.zip | |
clk: renesas: r8a7796: Add DRIF clock
This patch adds DRIF module clocks for r8a7796 SoC.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions