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| author |   Terry Bowman <terry.bowman@amd.com> | 2023-10-18 19:17:09 +0200 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2023-10-27 20:13:38 -0700 |
| commit | d1a9def33d7043df7445114cb89c0aa65818ae91 (patch) | |
| tree | 997667db73a4a07194c67618797a8c26eea954c6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | cxl/pci: Add RCH downstream port error logging (diff) | |
| download | wireguard-linux-d1a9def33d7043df7445114cb89c0aa65818ae91.tar.xz wireguard-linux-d1a9def33d7043df7445114cb89c0aa65818ae91.zip | |
cxl/pci: Disable root port interrupts in RCH mode
The RCH root port contains root command AER registers that should not be
enabled.[1] Disable these to prevent root port interrupts.
[1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-17-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions