diff options
| author |   Vineet Gupta <vgupta@kernel.org> | 2024-03-27 22:19:25 -0700 |
|---|---|---|
| committer | Vineet Gupta <vgupta@kernel.org> | 2024-04-01 18:40:39 -0700 |
| commit | d5272aaa8257920c7b398f953ada65e25c248f9a (patch) | |
| tree | 9d0318884cfe44c0761fc81d7acdadf7f5abf85b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARC: Fix -Wmissing-prototypes warnings (diff) | |
| download | wireguard-linux-d5272aaa8257920c7b398f953ada65e25c248f9a.tar.xz wireguard-linux-d5272aaa8257920c7b398f953ada65e25c248f9a.zip | |
ARC: mm: fix new code about cache aliasing
Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() across all architectures")
Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).
Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) [1] however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.
[1] http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html
Acked-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions