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| author |   Jason Gunthorpe <jgg@mellanox.com> | 2020-03-13 11:11:07 -0300 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@mellanox.com> | 2020-03-13 11:11:07 -0300 |
| commit | d613bd64c68bab6712c472281e79559bdc984b62 (patch) | |
| tree | 16851e5c0dda8f01696b02bde8ba128012830911 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RDMA/cm: Delete not implemented CM peer to peer communication (diff) | |
| parent | RDMA/mlx5: Allow MRs to be created in the cache synchronously (diff) | |
| download | wireguard-linux-d613bd64c68bab6712c472281e79559bdc984b62.tar.xz wireguard-linux-d613bd64c68bab6712c472281e79559bdc984b62.zip | |
Merge branch 'mlx5_mr_cache' into rdma.git for-next
Leon Romanovsky says:
====================
This series fixes various corner cases in the mlx5_ib MR cache
implementation, see specific commit messages for more information.
====================
Based on the mlx5-next branch at
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
Due to dependencies
* branch 'mlx5_mr-cache':
RDMA/mlx5: Allow MRs to be created in the cache synchronously
RDMA/mlx5: Revise how the hysteresis scheme works for cache filling
RDMA/mlx5: Fix locking in MR cache work queue
RDMA/mlx5: Lock access to ent->available_mrs/limit when doing queue_work
RDMA/mlx5: Fix MR cache size and limit debugfs
RDMA/mlx5: Always remove MRs from the cache before destroying them
RDMA/mlx5: Simplify how the MR cache bucket is located
RDMA/mlx5: Rename the tracking variables for the MR cache
RDMA/mlx5: Replace spinlock protected write with atomic var
{IB,net}/mlx5: Move asynchronous mkey creation to mlx5_ib
{IB,net}/mlx5: Assign mkey variant in mlx5_ib only
{IB,net}/mlx5: Setup mkey variant before mr create command invocation
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions