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| author |   Dillon Varone <Dillon.Varone@amd.com> | 2022-09-28 15:44:38 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-10-10 17:32:55 -0400 |
| commit | d6170e418d1d3ae7e98cb6d96d1444e880131bbf (patch) | |
| tree | f87db9ab14d36164c27c2c05a372fec57fc4a812 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Validate DSC After Enable All New CRTCs (diff) | |
| download | wireguard-linux-d6170e418d1d3ae7e98cb6d96d1444e880131bbf.tar.xz wireguard-linux-d6170e418d1d3ae7e98cb6d96d1444e880131bbf.zip | |
drm/amd/display: Acquire FCLK DPM levels on DCN32
[Why & How]
Acquire FCLK DPM levels to properly construct DML clock limits. Further
add new logic to keep number of indices for each clock in clk_mgr.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions