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author | 2024-03-26 21:49:49 -0700 | |
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committer | 2024-04-29 10:49:31 -0700 | |
commit | d6dcdabafcd7c612b164079d00da6d9775863a0b (patch) | |
tree | 891257d2841136d48575cc49123a13f10974beb3 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma (diff) | |
download | wireguard-linux-d6dcdabafcd7c612b164079d00da6d9775863a0b.tar.xz wireguard-linux-d6dcdabafcd7c612b164079d00da6d9775863a0b.zip |
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
Implementations affected by SiFive errata CIP-1200 have a bug which
forces the kernel to always use the global variant of the sfence.vma
instruction. When affected by this errata, do not attempt to flush a
range of addresses; each iteration of the loop would actually flush the
whole TLB instead. Instead, minimize the overall number of sfence.vma
instructions.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Yunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20240327045035.368512-9-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions