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| author |   Vladimir Zapolskiy <vz@mleia.com> | 2016-04-25 04:00:23 +0300 |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2016-04-28 00:36:24 +0300 |
| commit | d839e821efc06031c927cabbbc1e976bc71f5d4f (patch) | |
| tree | 47547e13d0ebe3f89d728047db65fb197a5d19e9 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default (diff) | |
| download | wireguard-linux-d839e821efc06031c927cabbbc1e976bc71f5d4f.tar.xz wireguard-linux-d839e821efc06031c927cabbbc1e976bc71f5d4f.zip | |
dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions