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| author |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-09 15:02:50 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-12 09:48:58 -0700 |
| commit | da411a48bdeb648153dc9a485c15c18f3d063eac (patch) | |
| tree | 3d63f856ee22c8f2db86b480344f1921d6ed928e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/cnl: Enable wrpll computation for CNL (diff) | |
| download | wireguard-linux-da411a48bdeb648153dc9a485c15c18f3d063eac.tar.xz wireguard-linux-da411a48bdeb648153dc9a485c15c18f3d063eac.zip | |
drm/i915/cfl: Basic DDI plumbing for Coffee Lake.
All here is pretty much like Kabylake.
Including CFL-U has to use same ddi translation table
as KBL-U for now.
v2: Include missed IS_COFFEELAKE on edp trans table. (DK)
Handle CFL-U with same translation table as KBL-U. (DK and
confirmed with HW engineers)
v3: Adding missed case for IS_CFL_ULT. (DK).
v4: Duh! Now with the real IS_CFL_ULT instead of KBL one. (DK)
Also use IS_GEN9_BC when possible. (DK)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions