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| author |   Zhen Lei <thunder.leizhen@huawei.com> | 2021-01-18 11:16:31 +0800 |
|---|---|---|
| committer |   Wei Xu <xuwei5@hisilicon.com> | 2021-01-29 16:33:25 +0800 |
| commit | dbbf51315a87e3fad6142bdce2278670d3e94e4b (patch) | |
| tree | f83a5443a4f9c809edf90e3e04884938439b0bf7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: hisilicon: place clock-names "bus" before "core" (diff) | |
| download | wireguard-linux-dbbf51315a87e3fad6142bdce2278670d3e94e4b.tar.xz wireguard-linux-dbbf51315a87e3fad6142bdce2278670d3e94e4b.zip | |
arm64: dts: hisilicon: normalize the node name of the module thermal
1. Change the node name of the thermal zone to match
'^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', add suffix "-thermal".
2. Change the node name of the trip point to match
'^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', delete character "@".
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions