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| author |   Charlie Jenkins <charlie@rivosinc.com> | 2024-01-08 15:57:04 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-17 17:52:31 -0800 |
| commit | e11e367e9fe57164ea609807ed27184c85263355 (patch) | |
| tree | 312cbe8e5587361b9be7375b14c77f1079fb8a29 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: Add static key for misaligned accesses (diff) | |
| download | wireguard-linux-e11e367e9fe57164ea609807ed27184c85263355.tar.xz wireguard-linux-e11e367e9fe57164ea609807ed27184c85263355.zip | |
riscv: Add checksum header
Provide checksum algorithms that have been designed to leverage riscv
instructions such as rotate. In 64-bit, can take advantage of the larger
register to avoid some overflow checking.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Xiao Wang <xiao.w.wang@intel.com>
Link: https://lore.kernel.org/r/20240108-optimize_checksum-v15-3-1c50de5f2167@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions