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| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2023-04-25 10:20:52 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-04-25 10:20:52 -0700 |
| commit | e3420f98f8984c4ffde72e6a877bccbcc9cad6b6 (patch) | |
| tree | 5793024bd1d0d2b38a6f2f6173fa18d732405aff /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'x86_acpi_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (diff) | |
| parent | x86/cpu: Add Xeon Emerald Rapids to list of CPUs that support PPIN (diff) | |
| download | wireguard-linux-e3420f98f8984c4ffde72e6a877bccbcc9cad6b6.tar.xz wireguard-linux-e3420f98f8984c4ffde72e6a877bccbcc9cad6b6.zip | |
Merge tag 'x86_cpu_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu model updates from Borislav Petkov:
- Add Emerald Rapids to the list of Intel models supporting PPIN
- Finally use a CPUID bit for split lock detection instead of
enumerating every model
- Make sure automatic IBRS is set on AMD, even though the AP bringup
code does that now by replicating the MSR which contains the switch
* tag 'x86_cpu_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu: Add Xeon Emerald Rapids to list of CPUs that support PPIN
x86/split_lock: Enumerate architectural split lock disable bit
x86/CPU/AMD: Make sure EFER[AIBRSE] is set
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions