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author | 2021-01-28 02:42:20 +0300 | |
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committer | 2021-02-02 16:31:14 -0600 | |
commit | e53bdfc009770950dd23023a096542beb5f7df97 (patch) | |
tree | 4d125b495a9ff87452925c8d58cd5aac082f3599 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | arm64: dts: qcom: Add basic devicetree support for SM8350-MTP board (diff) | |
download | wireguard-linux-e53bdfc009770950dd23023a096542beb5f7df97.tar.xz wireguard-linux-e53bdfc009770950dd23023a096542beb5f7df97.zip |
arm64: dts: qcom: sm8250: Add PCIe support
Add PCIe support for Qcom SM8250 SoC. This SoC has 3 PCIe Gen 3
instances based on Designware IP, out of which PCIe0 has 1 lane support
and the rest have 2 lane support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[DB: add ddrss_sf_tbu clock]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210127234221.947306-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions