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| author |   Haibo Chen <haibo.chen@nxp.com> | 2020-06-22 16:19:19 +0800 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2020-07-13 12:18:24 +0200 |
| commit | e81515556d76cc00272bded98ec8d1def6eb9e2c (patch) | |
| tree | 2927bff89b3c6be939b1668bee97da2a5834cde9 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mmc: sdhci_am654: Add support for clkbuf_sel property (diff) | |
| download | wireguard-linux-e81515556d76cc00272bded98ec8d1def6eb9e2c.tar.xz wireguard-linux-e81515556d76cc00272bded98ec8d1def6eb9e2c.zip | |
mmc: sdio: fix clock rate setting for SDR12/SDR25 mode
In current code logic, when work in SDR12/SDR25 mode, the final clock
rate is incorrect, just the legancy 400KHz, because the
card->sw_caps.sd3_bus_mode do not has the flag SD_MODE_UHS_SDR12 or
SD_MODE_UHS_SDR25. Besides, SDIO_SPEED_SDR12 is actually value 0, and
every mode need to config the timing and clock rate, so remove the
‘if’ operator.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Tested-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/1592813959-5914-1-git-send-email-haibo.chen@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions