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| author |   Cong Dang <cong.dang.xn@renesas.com> | 2024-02-11 15:22:46 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-20 11:32:35 +0100 |
| commit | e89ea92f533b3f4d52c8778ca544a06078d0d6f0 (patch) | |
| tree | 20179e2bb69326c5c683ffd3473d95f3be48f59b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable (diff) | |
| download | wireguard-linux-e89ea92f533b3f4d52c8778ca544a06078d0d6f0.tar.xz wireguard-linux-e89ea92f533b3f4d52c8778ca544a06078d0d6f0.zip | |
clk: renesas: r8a779h0: Add EtherAVB clocks
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on
the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions