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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-07-30 13:24:33 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:43:26 +0200 |
| commit | ec9532628eb9d82282b8e52fd9c4a3800d87feec (patch) | |
| tree | d2332158babcc67712f78e7e55888124a82d6e25 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r9a07g0{43,44,54}: Move regulator-vbus device node (diff) | |
| download | wireguard-linux-ec9532628eb9d82282b8e52fd9c4a3800d87feec.tar.xz wireguard-linux-ec9532628eb9d82282b8e52fd9c4a3800d87feec.zip | |
arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes
The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.
Despite the RZ/G3S SoC being single-core, it has two instances of GICR.
Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions