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| author |   Steve Shih <sshih@cisco.com> | 2016-10-17 09:51:05 -0700 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-10-27 16:41:56 +0200 |
| commit | ecb988a3b7985913d1f0112f66667cdd15e40711 (patch) | |
| tree | d06aea62155b4bc3bc4415f569b2b19f76991416 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | tty: limit terminal size to 4M chars (diff) | |
| download | wireguard-linux-ecb988a3b7985913d1f0112f66667cdd15e40711.tar.xz wireguard-linux-ecb988a3b7985913d1f0112f66667cdd15e40711.zip | |
tty: serial: 8250: 8250_core: NXP SC16C2552 workaround
NXP SC16C2552 requires that we always write a reset to the RX FIFO and
TX FIFO whenever we enable the FIFOs
Cc: xe-kernel@external.cisco.com
Signed-off-by: Steve Shih <sshih@cisco.com>
Signed-off-by: David Singleton <davsingl@cisco.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions