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| author |   Alan Douglas <adouglas@cadence.com> | 2018-11-12 16:42:01 +0000 |
|---|---|---|
| committer |   Rob Herring <robh@kernel.org> | 2018-11-16 16:28:04 -0600 |
| commit | f0001f587731603d2eccf5577ea74f12aa9a477c (patch) | |
| tree | 181ae07e4886f947cf15a32f6754a44c2c28557c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'kfree_validate_v7-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/frowand/linux into dt/next (diff) | |
| download | wireguard-linux-f0001f587731603d2eccf5577ea74f12aa9a477c.tar.xz wireguard-linux-f0001f587731603d2eccf5577ea74f12aa9a477c.zip | |
dt-bindings: phy: Document cadence Sierra PHY bindings
Add DT binding documentation for Sierra PHY. The PHY supports
a number of different protocols, including PCIe and USB.
The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node. For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.
There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link. For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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