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| author |   Duc Dang <dhdang@apm.com> | 2016-06-20 18:26:35 -0700 |
|---|---|---|
| committer | Duc Dang <dhdang@apm.com> | 2016-06-20 18:26:35 -0700 |
| commit | f0a78909bd6fc48c50d6557bac95a589d2f987d4 (patch) | |
| tree | e7ea986eca63316faba6002d14cd673fe441f2cd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: apm: Remove leading '0x' from unit addresses (diff) | |
| download | wireguard-linux-f0a78909bd6fc48c50d6557bac95a589d2f987d4.tar.xz wireguard-linux-f0a78909bd6fc48c50d6557bac95a589d2f987d4.zip | |
arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <dhdang@apm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions