aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-postgresql.py
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2016-11-17 23:29:20 -0800
committerOlof Johansson <olof@lixom.net>2016-11-17 23:29:20 -0800
commitf17ccd11a0034cca18236383fcd00ec62c5de8ad (patch)
tree0abd9b2f66e88d29553fc43b0aa47385dd158263 /tools/perf/scripts/python/export-to-postgresql.py
parentMerge tag 'sti-dt-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/dt (diff)
parentARM: dts: socfpga: add nand controller nodes (diff)
downloadwireguard-linux-f17ccd11a0034cca18236383fcd00ec62c5de8ad.tar.xz
wireguard-linux-f17ccd11a0034cca18236383fcd00ec62c5de8ad.zip
Merge tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS update for v4.10, part 2 - Add specific compatible strings for variants of Cyclone5 boards - Add QSPI node on Arria10 - Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit - Add NAND controller node on Cyclone5 * tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: add nand controller nodes ARM: dts: socfpga: Enable QSPI on the Arria5 devkit ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit ARM: dts: socfpga: Enable QSPI in Arria10 devkit ARM: dts: socfpga: Add QSPI node for the Arria10 ARM: dts: socfpga: enable qspi on the Cyclone5 devkit ARM: dts: socfpga: add specific compatible strings for boards Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions