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author | 2023-05-16 15:52:05 +0200 | |
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committer | 2023-06-12 18:20:04 -0700 | |
commit | f235f6ae59e5060af6d924038348f94a6348ee8d (patch) | |
tree | 1b285646e19ac33b18fb003f39f29aebadec6efc /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag (diff) | |
download | wireguard-linux-f235f6ae59e5060af6d924038348f94a6348ee8d.tar.xz wireguard-linux-f235f6ae59e5060af6d924038348f94a6348ee8d.zip |
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions