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| author |   Andre Przywara <andre.przywara@arm.com> | 2020-08-28 14:05:56 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2020-08-31 13:52:59 +0800 |
| commit | f2dc2359b75e1fd345fd710862f73db20dc55864 (patch) | |
| tree | b655dd933ccad27a0afe7b2eba0ad96453e68274 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: imx8mm-var-som-symphony: Add Variscite Symphony board with VAR-SOM-MX8MM (diff) | |
| download | wireguard-linux-f2dc2359b75e1fd345fd710862f73db20dc55864.tar.xz wireguard-linux-f2dc2359b75e1fd345fd710862f73db20dc55864.zip | |
arm64: dts: freescale: Fix SP805 clock-names
The SP805 binding sets the order of the clock-names to be: "wdog_clk",
"apb_pclk" (in exactly that order).
Change the order in the DTs for Freescale platforms to match that. The
two clocks given in all nodes are actually the same, so that does not
change any behaviour.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions