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author | 2023-07-27 14:20:11 -0700 | |
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committer | 2023-08-07 14:19:16 -0700 | |
commit | f30a648d87485174700cd91e54fada5df5691a77 (patch) | |
tree | 109333969a7bc1bd80b3dff53c9a3393999ceaa6 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/msm/adreno: Use quirk to identify cached-coherent support (diff) | |
download | wireguard-linux-f30a648d87485174700cd91e54fada5df5691a77.tar.xz wireguard-linux-f30a648d87485174700cd91e54fada5df5691a77.zip |
drm/msm/adreno: Allow SoC specific gpu device table entries
There are cases where there are differences due to SoC integration.
Such as cache-coherency support, and (in the next patch) e-fuse to
speedbin mappings.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549767/
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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